1. Field of the Invention
The present invention generally relates to electronic circuits designed for semiconductor integrated circuit manufacturing, and more particularly to an electronic circuit for dynamically calibrating an analog to digital converter.
2. Description of the Related Art
Low voltage all CMOS flash Analog to Digital Converters (ADC) face the competing requirements of speed and accuracy. On one hand, conversion rates are in the multi-Gigasample per second range. On the other hand, decreasing power supply voltages require that comparators must discriminate between analog signals separated by mere millivolts. As a result, the small device sizes required and the process variations associated with semiconductor integrated circuit manufacturing necessitate the need for the calibration of Analog to Digital Converters for gain, offset, and symmetry to minimize non-idealities.
Calibration has typically been accomplished with the clocked portion of the flash ADC held in a fixed state, while the gain or offset of the front end is adjusted in response to the result of a DC or quasi-static comparison between an output and a reference. This method accomplishes calibration of the DC offset and DC gain, but does not address the dynamic offset or dynamic gain of the full ADC under normal operating conditions, which includes the clocking of the ADC back end.
To accomplish DC or quasi-static calibration automatically, one method in use, as described in U.S. Pat. No. 6,226,562, the complete disclosure of which is herein incorporated by reference, involves a generic calibrate engine for calibrating the analog circuits on a chip, where the output of an analog circuit is coupled into the input of a separate precision analog comparator that functions only during calibration. During calibration of the analog circuit, the output of the precision analog comparator is fed into the input of the calibration engine that drives the calibration. Thus, a separate precision analog comparator that adds design time, space, and manufacturing cost is needed.
U.S. Pat. No. 5,990,814, the complete disclosure of which is herein incorporated by reference, describes a calibration method for compensating both static and dynamic offsets of individual single-stage or multi-stage comparators while the comparator is operating in an ADC under normal operating conditions, including ADC clocking and control signals. This method incrementally adjusts the threshold value of each comparator. Thus, each individual component is calibrated, not the entire ADC system or unit. Therefore, this method cannot be used to correct the overall gain or overall offset of the ADC.
Thus, in light of the shortcoming of the conventional calibration methods, there exists a need for a new and improved circuit and method for dynamic calibration of flash analog to digital converters as an entire system or unit.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional calibration methods, the present invention has been devised, and it is an object of the present invention to provide a circuit and method for dynamically calibrating an analog to digital converter. It is another object of the present invention to calibrate the entire ADC as a system or unit. Another object of the present invention is to calibrate the overall gain and overall offset of the system. Yet another object of the present invention is to calibrate the ADC in its operational mode. Another object of the present invention is to calibrate the ADC based on the binary encoded output codes that are the output of the ADC system.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention, a circuit and method for dynamically calibrating an analog to digital converter (ADC), wherein the circuit comprises means for providing a signal having a known binary value representation to the ADC; and means for altering the gain or other parameters of the ADC to provide the known binary value.
Furthermore, the invention includes a method for dynamically calibrating an analog to digital converter, the method comprises inputting an input signal into a plurality of comparators; monitoring a binary encoded output code; detecting a calibration target for the output code; calibrating an overall system gain; and calibrating an overall system offset.
More precisely, a circuit for dynamically calibrating an analog to digital converter comprises a voltage source having an input voltage signal; a driver receiving the input voltage signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2nxe2x88x921 digital outputs; an encoding logic unit encoding the comparison result (2nxe2x88x921 digital outputs) into n digital bits as an output signal; a calibration engine connected to said encoding logic and receiving said output signal, and further outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver further receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit further receives the reference adjust signal, wherein the calibration engine receives n digital bits, and wherein said calibration engine controls an operation of said driver or said flash circuit based on said output signal.
The driver comprises a fixed or variable gain amplifier. The driver adjusts the driver output signal based on the driver offset adjust signal and the driver gain adjust signal. Moreover, the flash circuit adjusts internal reference voltages based on the reference adjust signal which effectively modifies the overall ADC gain. The calibration input circuit controls the input voltage signal into the driver based on the calibration input adjust signal. Additionally, the n digital bits comprise a feedback and determine the calibration input adjust signal, the reference adjust signal, the driver gain adjust signal, and the driver offset adjust signal.
The input voltage signal comprises a plurality of differential analog input signals. Also, the analog input signals are coupled to a high pass filter, wherein the high pass filter is coupled to a common mode control circuit, and wherein the common mode control circuit provides a reference voltage level.
Furthermore, the high pass filter is coupled to a track and hold circuit comprising a clock signal, wherein the track and hold circuit samples the input voltage signal when the clock signal articulates into a hold polarity, and wherein differential outputs of the track and hold circuit are coupled into inputs of the driver.
Additionally, the flash circuit comprises 2nxe2x88x921 comparators and a ladder resistor string, wherein the ladder resistor string provides a series of differential reference voltages for the 2nxe2x88x921 comparators.
The flash circuit is coupled to an encoding logic unit which encodes the 2nxe2x88x921 digital outputs which are the comparison result from the flash circuit into n digital bits.
As mentioned, the entire ADC is calibrated as a system or unit. Thus, the overall gain and overall offset of the system are calibrated, as opposed to the gain or offset of individual component circuits in the ADC separated out from the system during calibration. Also, the ADC is calibrated as it is operated under normal conditions, with all comparators enabled and clocked at a rate within the normal operating range, with the driver and the T/H operational. The calibration engine monitors the n digital bits that are the ADC output signal, and automatically adjusts gain or offset until a specified programmable ADC output code target is met.